I. Field of the Disclosure
The technology of the disclosure relates to modeling output delay of a clocked storage element. For example, the output delay can be used to model delay of clocked storage elements in a circuit timing model.
II. Background
Timing analysis of circuits employing clocked storage elements can be used to determine the expected timings of circuit paths. The expected timings assist in identifying problem areas during the design phase and in advance of fabrication of the circuit. In this regard, modeling tools can be employed to simulate delay in logic transitions in clocked storage elements in a synthesized circuit design. To simulate delay, delay models are provided for the clocked storage elements in the modeling tool. The delay models simulate the delay between arrival of input data signals to clocked storage elements and output data signals generated in response. The model delay can be used to determine whether the circuit meets desired timing constraints, and thus if the circuit is likely to operate properly if fabricated according to the tested design. For example, the delay may be used to determine if timings associated with one or more critical paths in a circuit are acceptable. If the circuit does not meet desired timing constraints, the circuit design can be altered and then reanalyzed using the modeling tool until desired timing constraints are met, prior to fabrication.
One example of a clocked storage element commonly employed in circuits is a latch. The latch may be designed to operate both transparently and non-transparently of the clock signal. If the input data arrives at the latch before the rising edge of a clock the latch will operate non-transparently of the clock signal. In non-transparent mode, the output delay of the latch is controlled by the clock signal since the rising edge of the clock signal arrives later than the input data. The latch may also be designed to operate transparently of the clock signal. In transparent mode, the output delay of the latch is controlled by the input data since the input data arrives later than the rising edge of the dock signal. This is also known as “time borrowing” or “cycle stealing.”
Two constant output delay values can be used by a modeling tool to simulate delay in a latch configured to operate in both non-transparent and transparent modes. However, if the input data arrives after the setup time of the latch when the latch is between non-transparent and transparent modes, a constant output delay value may not accurately reflect the output delay of the latch.